A novel clock-recovery method with superior performance has been developed for the reception of AES/EBU-EIAJ formatted serial digital audio data.
Current practices are exemplified in integrated circuits available from several manufacturers. For clock recovery, these devices all employ classical PLL methods using data edge-triggered digital phase detectors servoing voltage controlled oscillators of a convenient frequency with loop time constants determined by external RC networks. Typical examples for commercially available circuits using such clock recovery methods are YAMAHA YM3623B/3436B, PHILIPS SAA7274, CRYSTAL SEMICONDUCTOR CS8411/8412, and MOTOROLA DSP56401.
These commercially available circuits are used in audio data receivers. In prior art audio data receivers the recovered clock is corrupted by jitter (time displacement) resulting from the use of clock generating data signals.
More sophisticated designs have been used which supplement the internal phase-locked-loop amplifiers of these integrated circuits with external phase-locked-loop amplifiers, providing better performance at fs, the sampling frequency. However, even these more sophisticated designs are subject to data-induced jitter at any of their regenerated clocks.